Searched refs:CPOL (Results 1 – 7 of 7) sorted by relevance
424 new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0; in cs_activate()437 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; in cs_activate()444 if ((csr ^ cpol) & SPI_BIT(CPOL)) in cs_activate()446 csr ^ SPI_BIT(CPOL)); in cs_activate()1298 csr |= SPI_BIT(CPOL); in atmel_spi_setup()
30 #define CPOL BIT(2) macro410 cpol = CPOL; in setup_fifo_params()
52 spi-cpol; /* SPI mode: CPOL=1 */
100 - CPOL indicates the initial clock polarity. CPOL=0 means the102 the second (trailing) edge is falling. CPOL=1 means the clock113 but their timing diagrams will make the CPOL and CPHA modes clear.115 In the SPI mode number, CPOL is the high order bit and CPHA is the117 starting low (CPOL=0) and data stabilized for sampling during the
51 inverse clock polarity (CPOL) mode
71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */
1 The Code Project Open License (CPOL) 1.02