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Searched refs:CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c175 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v6_1_update_medium_grain_clock_gating()
183 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v6_1_update_medium_grain_clock_gating()
H A Dnbio_v7_2.c244 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v7_2_update_medium_grain_clock_gating()
251 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v7_2_update_medium_grain_clock_gating()
H A Dnbio_v2_3.c242 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v2_3_update_medium_grain_clock_gating()
249 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v2_3_update_medium_grain_clock_gating()
H A Dnbio_v4_3.c252 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
259 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h3677 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h44511 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro
H A Dnbio_4_3_0_sh_mask.h33936 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro
H A Dnbio_7_0_sh_mask.h75296 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro
H A Dnbio_2_3_sh_mask.h56032 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro
H A Dnbio_6_1_sh_mask.h39860 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro
H A Dnbio_7_2_0_sh_mask.h101568 #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK … macro