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Searched refs:CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h2447 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 macro
H A Dgfx_8_0_sh_mask.h1925 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11885 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h13315 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h13093 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h15096 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h3291 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h16326 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h18869 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h18569 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h17217 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK … macro