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Searched refs:CP15ISB (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/
H A Dbarriers.h26 #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) macro
37 #define ISB CP15ISB
H A Darmv7.h124 CP15ISB; in v7_enable_smp()
/openbmc/linux/arch/arm64/
H A DKconfig1769 The CP15 barrier instructions - CP15ISB, CP15DSB, and