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Searched refs:CP0_REG06__SRSCONF1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h327 #define CP0_REG06__SRSCONF1 2 macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5355 case CP0_REG06__SRSCONF1: in gen_mfc0()
6085 case CP0_REG06__SRSCONF1: in gen_mtc0()
6837 case CP0_REG06__SRSCONF1: in gen_dmfc0()
7551 case CP0_REG06__SRSCONF1: in gen_dmtc0()