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Searched refs:CP0_REG05__PWBASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h321 #define CP0_REG05__PWBASE 5 macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5325 case CP0_REG05__PWBASE: in gen_mfc0()
6055 case CP0_REG05__PWBASE: in gen_mtc0()
6807 case CP0_REG05__PWBASE: in gen_dmfc0()
7521 case CP0_REG05__PWBASE: in gen_dmtc0()