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Searched refs:CP0_MVPConf0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/mips/
H A Dmalta.c977 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, in malta_mips_config()
980 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, in malta_mips_config()
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c128 VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc1045 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
1054 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
H A Dcpu.h110 int32_t CP0_MVPConf0; member
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c236 return env->mvp->CP0_MVPConf0; in helper_mfc0_mvpconf0()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c8074 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mftr()
8300 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mttr()