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Searched refs:CP0SRSCtl_PSS (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h794 #define CP0SRSCtl_PSS 6 macro
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1178 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); in helper_mtc0_srsctl()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c1241 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); in gen_load_srsgpr()
1261 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); in gen_store_srsgpr()