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Searched refs:CP0SRSCtl_ESS (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h793 #define CP0SRSCtl_ESS 12 macro
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1178 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); in helper_mtc0_srsctl()