Home
last modified time | relevance | path

Searched refs:CP0SRSC3_SRS12 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h724 #define CP0SRSC3_SRS12 20 macro
H A Dcpu-defs.c.inc310 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |