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Searched refs:CP0SRSC1_SRS6 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h712 #define CP0SRSC1_SRS6 20 macro
H A Dcpu-defs.c.inc304 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |