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Searched refs:CP0SRSC1_SRS5 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.h713 #define CP0SRSC1_SRS5 10 macro
H A Dcpu-defs.c.inc305 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),