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Searched refs:CP0MVPC0_PVPE (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc1048 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
1050 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
H A Dcpu.h117 #define CP0MVPC0_PVPE 10 macro
/openbmc/qemu/hw/mips/
H A Dmalta.c981 CP0MVPC0_PVPE, 4, smp_cpus - 1); in malta_mips_config()