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Searched refs:CP0C5_MRP (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc445 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
760 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
800 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
H A Dcpu.h951 #define CP0C5_MRP 3 macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c15092 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; in mips_tr_init_disas_context()