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Searched refs:CP0C5_LLB (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc445 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
487 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
528 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
760 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
800 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
H A Dcpu.h950 #define CP0C5_LLB 4 macro