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Searched refs:CP0C3_VInt (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
170 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
212 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
234 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
256 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
282 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
331 (1 << CP0C3_VInt),
357 (1 << CP0C3_VInt),
381 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
406 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
[all …]
H A Dcpu.h906 #define CP0C3_VInt 5 macro