Searched refs:CP0C3_M (Results 1 – 3 of 3) sorted by relevance
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \382 (1 << CP0C3_M),407 (1 << CP0C3_M),436 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |484 (1 << CP0C3_RXI) | (1U << CP0C3_M),519 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |753 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |793 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |905 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |973 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
884 #define CP0C3_M 31 macro
399 #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \