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Searched refs:CP0C1_WR (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
479 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
601 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
622 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
650 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
679 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
706 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
727 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
751 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
791 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
[all …]
H A Dcpu.h869 #define CP0C1_WR 3 macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5602 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5620 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
6336 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6354 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
7078 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7096 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7797 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7815 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()