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Searched refs:CP0C1_IL (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
145 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
166 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
187 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
208 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
230 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
252 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
[all …]
H A Dcpu.h861 #define CP0C1_IL 19 /* 21..19 */ macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c1717 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && in check_nms_dl_il_sl_tl_l2c()