Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_DDR_SDRAM_BASE (Results 1 – 25 of 125) sorted by relevance

12345

/openbmc/u-boot/board/socrates/
H A Dtlb.c94 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
98 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
/openbmc/u-boot/board/freescale/c29xpcie/
H A Dtlb.c67 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
68 CONFIG_SYS_DDR_SDRAM_BASE,
71 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
72 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
/openbmc/u-boot/board/freescale/p1023rdb/
H A Dtlb.c86 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
87 CONFIG_SYS_DDR_SDRAM_BASE,
91 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
92 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
/openbmc/u-boot/board/freescale/p1022ds/
H A Dtlb.c76 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
80 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
81 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
/openbmc/u-boot/board/freescale/mpc8313erdb/
H A Dsdram.c50 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
60 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) in fixed_sdram()
64 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | in fixed_sdram()
65 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & in fixed_sdram()
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dtlb.c83 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
89 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
90 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dtlb.c103 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
106 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
107 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
/openbmc/u-boot/board/freescale/t102xqds/
H A Dtlb.c103 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
106 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
107 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
/openbmc/u-boot/board/freescale/t104xrdb/
H A Dtlb.c121 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
124 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
125 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
/openbmc/u-boot/include/configs/
H A Dls1012a_common.h23 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
25 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
27 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
H A Dls2080a_common.h44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL macro
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
161 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
H A Dls1088a_common.h52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL macro
54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
H A Dlx2160a_common.h29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL macro
37 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
53 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
H A Dnsim.h16 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
17 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
H A Dls1046a_common.h44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
198 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
H A Dtb100.h16 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
17 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
H A Daxs10x.h23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
H A Dls1043a_common.h44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
220 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
H A Dhsdk.h24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 macro
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/openbmc/u-boot/board/sbc8349/
H A Dsbc8349.c82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
89 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) in fixed_sdram()
93 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | in fixed_sdram()
94 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> in fixed_sdram()
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dddr.c71 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, in fixed_sdram()
81 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, in fixed_sdram()
88 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, in fixed_sdram()
96 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, in fixed_sdram()
/openbmc/u-boot/board/sbc8641d/
H A Dlaw.c31 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
32 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
/openbmc/u-boot/board/ve8313/
H A Dve8313.c41 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); in fixed_sdram()
51 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) in fixed_sdram()
55 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | in fixed_sdram()
56 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8349itx/
H A Dmpc8349itx.c37 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
39 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) in fixed_sdram()
43 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | in fixed_sdram()
44 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8349emds/
H A Dmpc8349emds.c94 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in fixed_sdram()
115 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) in fixed_sdram()
119 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | in fixed_sdram()
120 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> in fixed_sdram()

12345