Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_DDR_BLOCK2_BASE (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dls1012a_common.h28 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
H A Dls2080a_common.h47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL macro
H A Dls1088a_common.h55 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL macro
H A Dlx2160a_common.h31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL macro
H A Dls1046a_common.h47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
H A Dls1043a_common.h47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL macro
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dcpu.c1404 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; in dram_init_banksize()
1556 CONFIG_SYS_DDR_BLOCK2_BASE, in update_early_mmu_table()
1575 CONFIG_SYS_DDR_BLOCK2_BASE, in update_early_mmu_table()
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2300 CONFIG_SYS_DDR_BLOCK2_BASE