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Searched refs:CON1_PCW_CHG (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c23 #define CON1_PCW_CHG BIT(31) macro
132 val &= ~CON1_PCW_CHG; in mtk_pll_set_rate_regs()
135 val |= CON1_PCW_CHG; in mtk_pll_set_rate_regs()