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Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 25 of 27) sorted by relevance

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/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c127 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
213 CLK_TOP_UNIVPLL1_D2,
245 CLK_TOP_UNIVPLL1_D2
401 CLK_TOP_UNIVPLL1_D2,
443 CLK_TOP_UNIVPLL1_D2,
456 CLK_TOP_UNIVPLL1_D2,
H A Dclk-mt7629.c116 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
175 CLK_TOP_UNIVPLL1_D2,
319 CLK_TOP_UNIVPLL1_D2,
349 CLK_TOP_UNIVPLL1_D2,
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
324 <&topckgen CLK_TOP_UNIVPLL1_D2>;
392 <&topckgen CLK_TOP_UNIVPLL1_D2>;
468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h43 #define CLK_TOP_UNIVPLL1_D2 32 macro
H A Dmt7629-clk.h50 #define CLK_TOP_UNIVPLL1_D2 40 macro
H A Dmt7622-clk.h44 #define CLK_TOP_UNIVPLL1_D2 32 macro
H A Dmt6797-clk.h68 #define CLK_TOP_UNIVPLL1_D2 58 macro
H A Dmediatek,mt6795-clk.h71 #define CLK_TOP_UNIVPLL1_D2 60 macro
H A Dmt8173-clk.h73 #define CLK_TOP_UNIVPLL1_D2 63 macro
H A Dmt6765-clk.h58 #define CLK_TOP_UNIVPLL1_D2 23 macro
H A Dmediatek,mt8365-clk.h33 #define CLK_TOP_UNIVPLL1_D2 23 macro
H A Dmt2712-clk.h57 #define CLK_TOP_UNIVPLL1_D2 26 macro
H A Dmt2701-clk.h36 #define CLK_TOP_UNIVPLL1_D2 26 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h53 #define CLK_TOP_UNIVPLL1_D2 40 macro
H A Dmt7623-clk.h53 #define CLK_TOP_UNIVPLL1_D2 40 macro
/openbmc/u-boot/arch/arm/dts/
H A Dmt7629.dtsi97 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
263 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c427 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
H A Dclk-mt8173-topckgen.c506 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
H A Dclk-mt8135.c63 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
H A Dclk-mt7622.c286 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
H A Dclk-mt7629.c393 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
H A Dclk-mt6797.c48 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
H A Dclk-mt2712.c65 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
H A Dclk-mt8365.c52 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
H A Dclk-mt6765.c108 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),

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