Searched refs:CLK_TOP_SYSPLL_D5_D2 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 90 #define CLK_TOP_SYSPLL_D5_D2 54 macro
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8183.dtsi | 1180 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1259 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1286 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1299 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1372 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1385 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8183.c | 46 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
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