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Searched refs:CLK_TOP_MSDC50_0_HC_SEL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h81 #define CLK_TOP_MSDC50_0_HC_SEL 71 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8365.c433 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",