Home
last modified time | relevance | path

Searched refs:CLK_TOP_MSDC50_0_HCLK_SEL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro
H A Dmt2712-clk.h142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c661 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
H A Dclk-mt6765.c409 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",