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Searched refs:CLK_TOP_MSDC50_0 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h95 #define CLK_TOP_MSDC50_0 60 macro
H A Dmt8186-clk.h32 #define CLK_TOP_MSDC50_0 13 macro
H A Dmt6779-clk.h19 #define CLK_TOP_MSDC50_0 9 macro
H A Dmediatek,mt8188-clk.h38 #define CLK_TOP_MSDC50_0 27 macro
H A Dmt8195-clk.h42 #define CLK_TOP_MSDC50_0 30 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c536 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
H A Dclk-mt8188-topckgen.c1020 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
H A Dclk-mt8195-topckgen.c935 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
H A Dclk-mt6765.c143 FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
H A Dclk-mt6779.c691 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi1572 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1578 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
H A Dmt8195.dtsi1369 clocks = <&topckgen CLK_TOP_MSDC50_0>,