| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 81 #define CLK_TOP_MSDC30_1_SEL 70 macro
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| H A D | mt7629-clk.h | 96 #define CLK_TOP_MSDC30_1_SEL 86 macro
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| H A D | mt7622-clk.h | 81 #define CLK_TOP_MSDC30_1_SEL 69 macro
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| H A D | mediatek,mt6795-clk.h | 105 #define CLK_TOP_MSDC30_1_SEL 94 macro
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| H A D | mt8173-clk.h | 107 #define CLK_TOP_MSDC30_1_SEL 97 macro
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| H A D | mt6765-clk.h | 145 #define CLK_TOP_MSDC30_1_SEL 110 macro
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| H A D | mediatek,mt8365-clk.h | 85 #define CLK_TOP_MSDC30_1_SEL 75 macro
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| H A D | mt2712-clk.h | 144 #define CLK_TOP_MSDC30_1_SEL 113 macro
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| H A D | mt2701-clk.h | 102 #define CLK_TOP_MSDC30_1_SEL 91 macro
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| H A D | mt8192-clk.h | 37 #define CLK_TOP_MSDC30_1_SEL 25 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 100 #define CLK_TOP_MSDC30_1_SEL 86 macro
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| H A D | mt7623-clk.h | 113 #define CLK_TOP_MSDC30_1_SEL 99 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 474 TOP_MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x70, 24, 3, 31, 0),
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| H A D | clk-mt8173-topckgen.c | 554 MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
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| H A D | clk-mt8135.c | 366 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
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| H A D | clk-mt7622.c | 418 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
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| H A D | clk-mt7629.c | 491 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
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| H A D | clk-mt2712.c | 665 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
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| H A D | clk-mt8365.c | 446 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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| H A D | clk-mt8192.c | 608 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 525 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
661 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
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| H A D | clk-mt7629.c | 383 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7623.dtsi | 246 <&topckgen CLK_TOP_MSDC30_1_SEL>;
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622-rfb1.dts | 216 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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| H A D | mt7622-bananapi-bpi-r64.dts | 247 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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