Home
last modified time | relevance | path

Searched refs:CLK_TOP_HIF_SEL (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
321 <&topckgen CLK_TOP_HIF_SEL>;
389 <&topckgen CLK_TOP_HIF_SEL>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h108 #define CLK_TOP_HIF_SEL 94 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7629-clk.h104 #define CLK_TOP_HIF_SEL 94 macro
H A Dmt7622-clk.h89 #define CLK_TOP_HIF_SEL 77 macro
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c144 FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
146 FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
395 MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
/openbmc/u-boot/arch/arm/dts/
H A Dmt7629.dtsi94 clocks = <&topckgen CLK_TOP_HIF_SEL>;
96 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7622.c438 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
H A Dclk-mt7629.c509 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi251 clocks = <&topckgen CLK_TOP_HIF_SEL>;