| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 182 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
508 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
597 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
599 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
606 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
609 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
611 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
613 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
614 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
648 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
[all …]
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| H A D | clk-mt7629.c | 133 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
134 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
143 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
145 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
364 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
546 .muxes_offs = CLK_TOP_AXI_SEL,
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7629.dtsi | 187 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
200 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
213 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 73 #define CLK_TOP_AXI_SEL 62 macro
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| H A D | mt7629-clk.h | 83 #define CLK_TOP_AXI_SEL 73 macro
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| H A D | mt7622-clk.h | 68 #define CLK_TOP_AXI_SEL 56 macro
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| H A D | mediatek,mt6795-clk.h | 90 #define CLK_TOP_AXI_SEL 79 macro
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| H A D | mt8173-clk.h | 92 #define CLK_TOP_AXI_SEL 82 macro
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| H A D | mt6765-clk.h | 131 #define CLK_TOP_AXI_SEL 96 macro
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| H A D | mediatek,mt8365-clk.h | 71 #define CLK_TOP_AXI_SEL 61 macro
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| H A D | mt2712-clk.h | 130 #define CLK_TOP_AXI_SEL 99 macro
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| H A D | mt2701-clk.h | 90 #define CLK_TOP_AXI_SEL 79 macro
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| H A D | mt8192-clk.h | 12 #define CLK_TOP_AXI_SEL 0 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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| H A D | mt7623-clk.h | 101 #define CLK_TOP_AXI_SEL 87 macro
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| /openbmc/linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 267 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
319 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
388 <&topckgen CLK_TOP_AXI_SEL>,
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 462 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
571 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); in mtk_topckgen_init()
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| H A D | clk-mt6795-topckgen.c | 452 TOP_MUX_GATE_NOSR(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt8173-topckgen.c | 531 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
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| H A D | clk-mt8135.c | 354 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt7622.c | 386 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt2712.c | 644 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
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| H A D | clk-mt8365.c | 410 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6795.dtsi | 655 <&topckgen CLK_TOP_AXI_SEL>;
665 <&topckgen CLK_TOP_AXI_SEL>;
675 <&topckgen CLK_TOP_AXI_SEL>;
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| H A D | mt7622.dtsi | 260 <&topckgen CLK_TOP_AXI_SEL>;
716 <&topckgen CLK_TOP_AXI_SEL>;
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