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Searched refs:CLK_SYSREG (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos5250.h123 #define CLK_SYSREG 319 macro
H A Dexynos5420.h95 #define CLK_SYSREG 302 macro
H A Dexynos4.h180 #define CLK_SYSREG 342 macro
H A Dexynos3250.h164 #define CLK_SYSREG 158 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos4.c935 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
977 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
H A Dclk-exynos5250.c607 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
H A Dclk-exynos3250.c504 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
H A Dclk-exynos5420.c1113 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",