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Searched refs:CLK_SMMU_MFCL (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos5250.h71 #define CLK_SMMU_MFCL 267 macro
H A Dexynos5420.h137 #define CLK_SMMU_MFCL 402 macro
H A Dexynos4.h112 #define CLK_SMMU_MFCL 274 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c547 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
H A Dclk-exynos4.c828 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
H A Dclk-exynos5420.c1283 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4.dtsi886 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
H A Dexynos5250.dtsi872 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
H A Dexynos5420.dtsi1138 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;