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Searched refs:CLK_SEL (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/hw/misc/
H A Daspeed_scu.c28 #define CLK_SEL TO_REG(0x08) macro
183 [CLK_SEL] = 0xF3F40000U,
218 [CLK_SEL] = 0xF3F40000U,
267 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) in aspeed_2400_scu_get_apb_freq()
/openbmc/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c33 #define CLK_SEL 0x10 macro
702 data->clk_sel = readl(data->reg + CLK_SEL); in armada_3700_periph_clock_suspend()
718 writel(data->clk_sel, data->reg + CLK_SEL); in armada_3700_periph_clock_resume()
/openbmc/linux/drivers/staging/rts5208/
H A Drtsx_chip.c641 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); in rts5208_init()
644 retval = rtsx_read_register(chip, CLK_SEL, &val); in rts5208_init()
700 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); in rts5288_init()
703 retval = rtsx_read_register(chip, CLK_SEL, &val); in rts5288_init()
H A Drtsx_card.h821 #define CLK_SEL 0xFC04 macro
H A Drtsx_card.c795 retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel); in switch_normal_clock()
/openbmc/u-boot/drivers/clk/mvebu/
H A Darmada-37xx-periph.c23 #define CLK_SEL 0x10 macro
/openbmc/linux/include/linux/
H A Drtsx_pci.h457 #define CLK_SEL 0xFC04 macro