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Searched refs:CLK_PDMA1 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dexynos5410.h58 #define CLK_PDMA1 363 macro
H A Dexynos5250.h80 #define CLK_PDMA1 276 macro
H A Ds5pv210.h114 #define CLK_PDMA1 96 macro
H A Dexynos5420.h123 #define CLK_PDMA1 363 macro
H A Dexynos4.h131 #define CLK_PDMA1 293 macro
H A Dexynos3250.h206 #define CLK_PDMA1 200 macro
H A Dexynos5433.h561 #define CLK_PDMA1 64 macro
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5410.c185 GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
H A Dclk-s5pv210.c632 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
H A Dclk-exynos5250.c560 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
H A Dclk-exynos3250.c651 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
H A Dclk-exynos4.c841 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
H A Dclk-exynos5420.c1039 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
H A Dclk-exynos5433.c2351 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi205 clocks = <&clock CLK_PDMA1>;
H A Ds5pv210.dtsi135 clocks = <&clocks CLK_PDMA1>;
H A Dexynos3250.dtsi610 clocks = <&cmu CLK_PDMA1>;
H A Dexynos4.dtsi684 clocks = <&clock CLK_PDMA1>;
H A Dexynos5250.dtsi715 clocks = <&clock CLK_PDMA1>;
H A Dexynos5420.dtsi564 clocks = <&clock CLK_PDMA1>;
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1874 clocks = <&cmu_fsys CLK_PDMA1>;