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Searched refs:CLK_MM_MDP_WDMA0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c32 GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
H A Dclk-mt8183-mm.c54 GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h257 #define CLK_MM_MDP_WDMA0 6 macro
H A Dmt6779-clk.h382 #define CLK_MM_MDP_WDMA0 42 macro
H A Dmt8183-clk.h350 #define CLK_MM_MDP_WDMA0 41 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi1716 clocks = <&mmsys CLK_MM_MDP_WDMA0>;