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Searched refs:CLK_MCU_MP0_SEL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h289 #define CLK_MCU_MP0_SEL 0 macro
H A Dmt8183-clk.h421 #define CLK_MCU_MP0_SEL 0 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8183.c611 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
H A Dclk-mt2712.c782 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi334 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
357 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
380 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
403 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
H A Dmt2712e.dtsi89 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
102 clocks = <&mcucfg CLK_MCU_MP0_SEL>,