Searched refs:CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK (Results 1 – 2 of 2) sorted by relevance
194 #define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 macro
1210 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,