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Searched refs:CLK_DIV_TOP1_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h622 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ macro
794 #define CLK_DIV_TOP1_VAL 0x13100B00 macro
H A Dclock_init_exynos5.c699 writel(CLK_DIV_TOP1_VAL, &clk->div_top1); in exynos5250_system_clock_init()
920 writel(CLK_DIV_TOP1_VAL, &clk->div_top1); in exynos5420_system_clock_init()