Home
last modified time | relevance | path

Searched refs:CLK_DIV_RIGHTBUS_VAL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c67 writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); in system_clock_init()
H A Dexynos4_setup.h170 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) macro
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c327 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); in board_clock_init()
H A Dsetup.h122 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) macro