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Searched refs:CLK_DIV_FSYS0_VAL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h488 #define CLK_DIV_FSYS0_VAL 0x0BB00000 macro
756 #define CLK_DIV_FSYS0_VAL 0x0 macro
H A Dclock_init_exynos5.c745 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); in exynos5250_system_clock_init()
941 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); in exynos5420_system_clock_init()