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Searched refs:CLK_BDP_WR_DI_PXL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2701-bdp.c60 GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
/openbmc/linux/include/dt-bindings/clock/
H A Dmt2701-clk.h458 #define CLK_BDP_WR_DI_PXL 27 macro