Searched refs:CICR (Results 1 – 7 of 7) sorted by relevance
/openbmc/qemu/include/hw/misc/ |
H A D | stm32l4x5_rcc_internals.h | 118 REG32(CICR, 0x20) 120 FIELD(CICR, LSECSSC, 9, 1) 121 FIELD(CICR, CSSC, 8, 1) 122 FIELD(CICR, PLLSAI2RDYC, 7, 1) 123 FIELD(CICR, PLLSAI1RDYC, 6, 1) 124 FIELD(CICR, PLLRDYC, 5, 1) 125 FIELD(CICR, HSERDYC, 4, 1) 126 FIELD(CICR, HSIRDYC, 3, 1) 127 FIELD(CICR, MSIRDYC, 2, 1) 128 FIELD(CICR, LSERDYC, 1, 1) [all …]
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/openbmc/linux/arch/arm/mach-omap2/ |
H A D | dma.c | 56 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
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/openbmc/linux/include/linux/ |
H A D | omap-dma.h | 153 CSDP, CCR, CICR, CSR, enumerator
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/openbmc/linux/arch/arm/mach-omap1/ |
H A D | omap-dma.c | 85 p->dma_write(0, CICR, lch); in omap_disable_channel_irq() 328 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); in omap_enable_channel_irq()
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H A D | dma.c | 58 [CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
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/openbmc/linux/drivers/net/wan/ |
H A D | wanxlfw.S | 92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config define 225 movel #0xD41F40 + (CPM_IRQ_LEVEL << 13), CICR
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/openbmc/linux/drivers/dma/ti/ |
H A D | omap-dma.c | 454 omap_dma_chan_write(c, CICR, cicr); in omap_dma_start() 491 omap_dma_chan_write(c, CICR, 0); in omap_dma_stop()
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