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Searched refs:CFG_REG_0_OFFSET (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Ddra7xx_iodelay.c62 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, in calibrate_iodelay()
65 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) in calibrate_iodelay()
74 clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, in update_delay_mechanism()
77 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) in update_delay_mechanism()
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Ddra7xx_iodelay.h16 #define CFG_REG_0_OFFSET 0xC macro