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Searched refs:CCR_CACHE_INIT (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7750.h14 #define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ macro
17 #define CCR_CACHE_INIT 0x0000090B macro
H A Dcpu_sh7763.h12 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7706.h5 #define CCR_CACHE_INIT 0x0000000D macro
H A Dcpu_sh7710.h5 #define CCR_CACHE_INIT 0x0000000D macro
H A Dcpu_sh7734.h14 #define CCR_CACHE_INIT 0x0000090d macro
H A Dcpu_sh7785.h12 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7723.h12 #define CCR_CACHE_INIT 0x0000090d macro
H A Dcpu_sh7724.h12 #define CCR_CACHE_INIT 0x0000090d macro
H A Dcpu_sh7757.h11 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7752.h11 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7753.h11 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7720.h16 #define CCR_CACHE_INIT 0x0000000B macro
H A Dcpu_sh7780.h11 #define CCR_CACHE_INIT 0x0000090b macro
H A Dcpu_sh7722.h12 #define CCR_CACHE_INIT 0x0000090d macro
/openbmc/u-boot/arch/sh/cpu/sh4/
H A Dcache.c50 outl(CCR_CACHE_INIT, CCR); in cache_control()
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dlowlevel_init.S414 CCR_D: .long CCR_CACHE_INIT
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dlowlevel_init.S445 CCR_D: .long CCR_CACHE_INIT
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dlowlevel_init.S544 CCR_D: .long CCR_CACHE_INIT