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Searched refs:CACHEATTR (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/xtensa/
H A Dmmu_helper.c433 env->sregs[CACHEATTR] = 0x22222222; in reset_mmu()
1075 *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> in xtensa_get_physical_addr()
H A Dcpu.h133 CACHEATTR = 98, enumerator
H A Dtranslate.c3789 CACHEATTR,
4700 CACHEATTR,
5465 CACHEATTR,