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/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
/openbmc/linux/arch/x86/events/zhaoxin/
H A Dcore.c51 [C(L1D)] = {
52 [C(OP_READ)] = {
53 [C(RESULT_ACCESS)] = 0x0042,
54 [C(RESULT_MISS)] = 0x0538,
56 [C(OP_WRITE)] = {
57 [C(RESULT_ACCESS)] = 0x0043,
58 [C(RESULT_MISS)] = 0x0562,
60 [C(OP_PREFETCH)] = {
61 [C(RESULT_ACCESS)] = -1,
62 [C(RESULT_MISS)] = -1,
[all …]
/openbmc/linux/arch/powerpc/perf/
H A Dpower10-pmu.c351 #define C(x) PERF_COUNT_HW_CACHE_##x macro
358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = 0,
366 [C(RESULT_MISS)] = PM_ST_MISS_L1,
368 [C(OP_PREFETCH)] = {
[all …]
H A Dgeneric-compat-pmu.c178 #define C(x) PERF_COUNT_HW_CACHE_##x macro
185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
188 [ C(RESULT_ACCESS) ] = 0,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
191 [ C(OP_WRITE) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
195 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower8-pmu.c259 #define C(x) PERF_COUNT_HW_CACHE_##x macro
266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = 0,
274 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
276 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower9-pmu.c330 #define C(x) PERF_COUNT_HW_CACHE_##x macro
337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
341 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = 0,
345 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
347 [ C(OP_PREFETCH) ] = {
[all …]
H A De6500-pmu.c28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
H A De500-pmu.c27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/hddtemp/hddtemp/
H A Dhddtemp.db6 # a temperature sensor (you can set the unit to C or F).
46 "ExcelStor Technology J3.0" 194 C "ExcelStor Technology 3xy (xy GB)"
47 "ExcelStor Technology J6.0" 194 C "ExcelStor Technology 6xy (xy GB)"
48 "ExcelStor Technology J680" 194 C "ExcelStor Technology J680 (80 GB)"
49 "ExcelStor Technology J860" 194 C "ExcelStor Technology J860 (60 GB)"
50 "ExcelStor Technology J880" 194 C "ExcelStor Technology J880 (80 GB)"
57 "FUJITSU MHM2100AT" 0 C "Fujitsu MHM2100AT"
59 "FUJITSU MHN2150AT" 194 C "Fujitsu MHN2150AT"
60 "FUJITSU MHN2200AT" 194 C "Fujitsu MHN2200AT"
61 "FUJITSU MHN2300AT" 194 C "Fujitsu MHN2300AT"
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v7.c179 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
182 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
184 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
185 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
187 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
189 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
190 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
/openbmc/linux/arch/x86/events/intel/
H A Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
30 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
31 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
33 [ C(OP_WRITE) ] = {
34 [ C(RESULT_ACCESS) ] = 0,
35 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
37 [ C(OP_PREFETCH) ] = {
38 [ C(RESULT_ACCESS) ] = 0,
39 [ C(RESULT_MISS) ] = 0,
[all …]
H A Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
32 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
34 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
38 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
42 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
H A Dcore.c481 [ C(L1D ) ] = {
482 [ C(OP_READ) ] = {
483 [ C(RESULT_ACCESS) ] = 0x81d0,
484 [ C(RESULT_MISS) ] = 0xe124,
486 [ C(OP_WRITE) ] = {
487 [ C(RESULT_ACCESS) ] = 0x82d0,
490 [ C(L1I ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_MISS) ] = 0xe424,
494 [ C(OP_WRITE) ] = {
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/openbmc/linux/arch/sparc/kernel/
H A Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/openbmc/linux/drivers/perf/
H A Driscv_pmu_sbi.c122 #define C(x) PERF_COUNT_HW_CACHE_##x macro
126 [C(L1D)] = {
127 [C(OP_READ)] = {
128 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
129 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
130 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
131 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
133 [C(OP_WRITE)] = {
134 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
135 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
1010 [C(L1D)] = {
1017 [C(OP_READ)] = {
1018 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1019 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1021 [C(OP_WRITE)] = {
1022 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1023 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1026 [C(L1I)] = {
1027 [C(OP_READ)] = {
[all …]
/openbmc/linux/arch/x86/events/amd/
H A Dcore.c31 [ C(L1D) ] = {
32 [ C(OP_READ) ] = {
33 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
34 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0,
38 [ C(RESULT_MISS) ] = 0,
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
42 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/openbmc/linux/kernel/trace/
H A Dtrace_probe.h469 C(FILE_NOT_FOUND, "Failed to find the given file"), \
470 C(NO_REGULAR_FILE, "Not a regular file"), \
471 C(BAD_REFCNT, "Invalid reference counter offset"), \
472 C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \
473 C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \
474 C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \
475 C(BAD_MAXACT_TYPE, "Maxactive is only for function exit"), \
476 C(BAD_MAXACT, "Invalid maxactive number"), \
477 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
478 C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \
[all …]
/openbmc/linux/lib/zstd/common/
H A Dcpu.h97 #define C(name, bit) X(name, f1c, bit) macro
98 C(sse3, 0)
99 C(pclmuldq, 1)
100 C(dtes64, 2)
101 C(monitor, 3)
102 C(dscpl, 4)
103 C(vmx, 5)
104 C(smx, 6)
105 C(eist, 7)
106 C(tm2, 8)
[all …]
/openbmc/u-boot/lib/
H A Dsha1.c70 unsigned long temp, W[16], A, B, C, D, E; in sha1_process() local
103 C = ctx->state[2]; in sha1_process()
110 P (A, B, C, D, E, W[0]); in sha1_process()
111 P (E, A, B, C, D, W[1]); in sha1_process()
112 P (D, E, A, B, C, W[2]); in sha1_process()
113 P (C, D, E, A, B, W[3]); in sha1_process()
114 P (B, C, D, E, A, W[4]); in sha1_process()
115 P (A, B, C, D, E, W[5]); in sha1_process()
116 P (E, A, B, C, D, W[6]); in sha1_process()
117 P (D, E, A, B, C, W[7]); in sha1_process()
[all …]

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