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Searched refs:BUS_WIDTH_IN_BITS (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c15 u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
18 u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];
101 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
106 bit + pup * BUS_WIDTH_IN_BITS], in ddr3_tip_pbs()
219 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
225 BUS_WIDTH_IN_BITS], in ddr3_tip_pbs()
235 bit = BUS_WIDTH_IN_BITS; in ddr3_tip_pbs()
270 bit = BUS_WIDTH_IN_BITS; in ddr3_tip_pbs()
378 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
380 result_all_bit[bit + pup * BUS_WIDTH_IN_BITS + in ddr3_tip_pbs()
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H A Dddr3_training_centralization.c58 u8 cur_start_win[BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
59 u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
60 u8 cur_end_win[BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
61 u8 current_window[BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
63 u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
169 for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; in ddr3_tip_centralization()
222 bit_id < BUS_WIDTH_IN_BITS; in ddr3_tip_centralization()
498 u8 cur_start_win[BUS_WIDTH_IN_BITS]; in ddr3_tip_special_rx()
499 u8 cur_end_win[BUS_WIDTH_IN_BITS]; in ddr3_tip_special_rx()
585 for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) { in ddr3_tip_special_rx()
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H A Dddr3_training_ip_engine.c16 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
18 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
321 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search + in ddr3_tip_get_buf_ptr()
322 interface_num * MAX_BUS_NUM * BUS_WIDTH_IN_BITS]; in ddr3_tip_get_buf_ptr()
494 mask_dq_num_of_regs = octets_per_if_num * BUS_WIDTH_IN_BITS; in ddr3_tip_ip_training()
654 for (i = 0; i < BUS_WIDTH_IN_BITS; i++) { in ddr3_tip_process_result()
665 for (i = 0; i < BUS_WIDTH_IN_BITS; i++) { in ddr3_tip_process_result()
763 start_reg = pup_cnt * BUS_WIDTH_IN_BITS; in ddr3_tip_read_training_result()
764 end_reg = (pup_cnt + 1) * BUS_WIDTH_IN_BITS - 1; in ddr3_tip_read_training_result()
767 pup_cnt * BUS_WIDTH_IN_BITS + bit_num; in ddr3_tip_read_training_result()
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H A Dddr3_training_ip_flow.h19 #define BUS_WIDTH_IN_BITS 8 macro
H A Dddr3_training.c2602 bit_end = BUS_WIDTH_IN_BITS - 1; in ddr3_tip_is_pup_lock()
2624 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) { in ddr3_tip_get_buf_min()
2640 for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) { in ddr3_tip_get_buf_max()