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Searched refs:BR0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A DKconfig92 hex "Preliminary value for BR0"
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h18 #define BR0 0x5000 /* Register offset to immr */ macro
/openbmc/u-boot/include/
H A Dppc_asm.tmpl103 #define BR0 0x00000100
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S1169 lwz r4, BR0(r3)
1175 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
/openbmc/u-boot/
H A DREADME3132 Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)