Home
last modified time | relevance | path

Searched refs:BIT8 (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h206 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
235 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
H A Dhal_com_reg.h555 #define RRSR_24M BIT8
707 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
723 #define IMR_CPWM BIT8
754 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
H A Dosdep_service.h25 #define BIT8 0x00000100 macro
H A Drtw_mlme_ext.h52 #define DYNAMIC_BB_PWR_TRAIN BIT8 /* ODM_BB_PWR_TRAIN */
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h114 #define IMR_HIGHDOK BIT8
189 #define RRSR_24M BIT8
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h39 #define BIT8 0x00000100 macro
H A Dhalbtcoutsrc.h100 #define ALGO_TRACE_SW_DETAIL BIT8
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h395 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
424 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
H A Drtl8723b_phycfg.c133 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
135 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
H A Dodm.h373 ODM_BB_PWR_TRAIN = BIT8,
399 ODM_RTL8723B = BIT8,
H A Dodm_DIG.c22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
/openbmc/libcper/include/libcper/
H A DCper.h295 #define EFI_GENERIC_ERROR_PROC_ID_VALID BIT8
540 #define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8
885 #define EFI_PLATFORM_MEMORY_ROW_VALID BIT8
961 #define EFI_PLATFORM_MEMORY2_ROW_VALID BIT8
1123 #define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID BIT8
/openbmc/linux/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h18 #define BIT8 0x00000100 macro
/openbmc/linux/include/uapi/linux/
H A Dsynclink.h27 #define BIT8 0x0100 macro
/openbmc/linux/drivers/scsi/
H A Ddc395x.h68 #define BIT8 0x00000100 macro
/openbmc/linux/drivers/tty/
H A Dsynclink_gt.c387 #define IRQ_RXOVER BIT8
2283 if (gsr & (BIT8 << i)) in slgt_interrupt()
4033 val |= BIT8; in async_mode()
4073 val |= BIT8; in async_mode()
4122 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()
4195 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4268 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4912 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dreg.h366 #define RRSR_24M BIT8
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_hw4.h775 #define LPFC_SLI4_INTR8 BIT8