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Searched refs:ATTR05__ATTR_PAL_MASK (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h390 #define ATTR05__ATTR_PAL_MASK 0x0000003fL macro
H A Ddce_8_0_sh_mask.h10889 #define ATTR05__ATTR_PAL_MASK 0x3f macro
H A Ddce_10_0_sh_mask.h11273 #define ATTR05__ATTR_PAL_MASK 0x3f macro
H A Ddce_11_0_sh_mask.h11085 #define ATTR05__ATTR_PAL_MASK 0x3f macro
H A Ddce_11_2_sh_mask.h12339 #define ATTR05__ATTR_PAL_MASK 0x3f macro
H A Ddce_12_0_sh_mask.h64734 #define ATTR05__ATTR_PAL_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27455 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h45482 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_2_1_0_sh_mask.h48759 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h48701 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_1_0_sh_mask.h46395 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h52882 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h51962 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h54694 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h54502 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h390 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h63080 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h60006 #define ATTR05__ATTR_PAL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h48703 #define ATTR05__ATTR_PAL_MASK … macro